The present disclosure relates to a III-V semiconductor device on a group IV semiconductor substrate. Further, the present disclosure relates to a method for manufacturing a III-V semiconductor device on a group IV semiconductor substrate.
A variety of electronic and optoelectronic devices can be enabled by developing thin film relaxed lattice constant III-V semiconductors on silicon (Si) substrates. Surface layers capable of achieving the performance advantages of III-V materials may host a variety of high performance electronic devices, such as CMOS and quantum well (QW) transistors fabricated from extreme high mobility materials such as, but not limited to, indium antimonide (InSb), indium gallium arsenide (InGaAs) and indium arsenide (InAs). Optical devices such as lasers, detectors and photovoltaics may also be fabricated from various other direct band gap materials, such as, but not limited to, gallium arsenide (GaAs) and indium gallium arsenide (InGaAs). These devices can be further enhanced by integrating them on the same substrate with conventional devices of silicon.
Despite all these advantages, the growth of III-V materials upon silicon substrates presents many challenges. Crystal defects are generated by lattice mismatch, polar-on nonpolar mismatch, and thermal mismatch between the III-V semiconductor epitaxial layer and the silicon semiconductor substrate. Many defects, particularly threading dislocations and twins, tend to propagate into the “device layers” where the III-V semiconductor device is fabricated. Generally, the severity of defect generation correlates to the amount of lattice mismatch between the III-V semiconductor and the silicon substrate.
Various buffer layers have been used in attempts to relieve the strain induced by the lattice mismatch between the silicon substrate and the III-V device layer and to thereby reduce the detrimental defect density of the device layer. Viable solutions have been developed for growing III-V materials in wide trenches (or trenches with a width greater than 100 nm), however forming high quality crystalline III-V materials in sub-50 nm trenches required by the continuous scaling of III-V devices on Si substrates remains an unsolved important challenge.